The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device, in which one block decoder controls two memory cell blocks, thus improving the level of integration.
In recent years, there is an increasing demand for semiconductor memory devices, enabling electrical program and erasure and not requiring a periodical refresh function. Further, in order to develop large-capacity memory devices capable of storing a high capacity of data, research has been done into a technique of higher integration of memory devices. Active research has been done into flash memory.
Flash memory is generally classified into NAND type flash memory and NOR type flash memory. NOR type flash memory has a structure in which memory cells are connected to bit lines and word lines independently and, therefore, has a good random access time. In contrast, NAND type flash memory has a structure in which a plurality of memory cells are connected in series and only one contact per cell string is required and therefore has good integration. Thus, the NAND type structure is generally used in high-integration flash memory.
In general, a flash memory device requires a block decoder for performing a memory cell array on a block basis in order to perform program, read, and erase operations on a memory cell.
FIG. 1 is a circuit diagram of a conventional flash memory device for illustrating a block decoder.
Referring to FIG. 1, a NAND gate ND1 receives address signals XA, XB, XC and XD and performs a NAND operation on the address signals. A NAND gate ND2 receives an output signal from the NAND gate ND1 and a program precharge signal PGMPREb, and performs a NAND operation on the signals. When at least one of the address signals XA, XB, XC and XD is in a low level, the NAND gate ND1 outputs a signal of a high level. When one or more of the output signal of the NAND gate ND1 and the program precharge signal PGMPREb is in a low level, the NAND gate ND2 outputs a signal of a high level.
A NAND gate ND3 performs a NAND operation on an output signal of the NAND gate ND2 and a block enable signal EN. When the block enable signal EN is in a low level, the NAND gate ND3 outputs a signal of a high level to turn on a transistor N2. Accordingly, a node Q1 is reset.
A transistor N1 is turned on in response to a precharge signal PRE, so that an output signal of the NAND gate ND2 is applied to the node Q1. A voltage level of the node Q1 serves as a block select signal BLKWL. Meanwhile, transistors N3 and N4 are turned on in response to first and second control signals GA and GB of a pumping voltage (Vpp) level, respectively, so that the pumping voltage Vpp is applied to the node Q1. Accordingly, a block switch 20 operates in response to a voltage level of the node Q1 (i.e., the block select signal BLKWL), so that global word lines GWL<31;0> and word lines of a memory cell array 30 are connected.